Evertz PPCBoot 1.00 build 577 7457 rev 1.2, 100 MHz bus, 1250 MHz core boot flash: manufacturer 00B000B0, device 00B300B3, 16777216 bytes LLLLlllluuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu 256MB of memory found DFCDL SRAM value = 0000049C testing main memory main memory: 268435456 bytes using ethernet port 1 LOADING PROGRAM SECTIONS 0 00000000 0030D018 00010000 0030D018 1 02000000 00000000 00320000 00000000 2 02000000 0AD90CA0 00320000 00066854 LOAD COMPLETED, ENTRY AT 3158 ENTRY AT 3158, STACK AT FFFFEE0 Starting 3000PPV main memory: 256 MB read only instruction space core frequency 1249875000 bus frequency 99990000 reconfigured SDRAM RdBuff reconfigured SDRAM arbiter SDRAM priority reconfigured IDMA Arbitration reset total memory = 268435456 bytes available memory = 52813824 bytes SR0 = 00000000 SR1 = 00000000 SR2 = 00000000 SR3 = 00000000 SR4 = 00000000 SR5 = 00000000 SR6 = 00000000 SR7 = 30000001 SR8 = 00000000 SR9 = 00000000 SR10 = 00000000 SR11 = 00000000 SR12 = 00000000 SR13 = 00000000 SR14 = 00000000 SR15 = 00000000 kernel initialised BOOTCODE STS = 00000000 ************************************************************* Starting 7787VIPPRO Copyright 2006, Evertz Microsystems Ltd. ************************************************************* NUM_ACTIVE_DISPLAYS = 2 L2 cache enabled L3 167MHz: L3CKSP=4, L3PSP=0 Performing L3 Cache Data Bit Walking Test...Complete. Performing L3 Cache Addr = Data Test...Complete. L3 Cache Testing Complete... No L3 cache errors occurred. L3 cache enabled at 167 MHz (L3CR=0x8EA20004) MSR 00000072 MSR 00001072 HID0 8492C1BC HID0 8482C1BC HID1 0001FC80 HID1 3001FC80 ICTRL 00000000 ICTRL 0C000100 L2CR 80000000 L2CR C0000000 L3CR 8EA20004 CPU Master control 00000B00 CPU Master control 00003B00 CPU Mode 00000050 MSSCR0 05188000 MSSCR0 05188000 CPU Configuration 020000FF CPU Configuration 060800FF Reset Sample (Low) 259EB1A2 Reset Sample (High) 00550560 spr 287=0x80020102 PVR spr1008=0x8482C1BC HID0 spr1009=0x3001FC80 HID1 spr1023=0x00000000 PIR spr1016=0x00000000 LDSTCR spr1014=0x05188000 MSSCR0 spr1015=0x00008000 MSSSR0 spr1011=0x0C000100 ICTRL spr1017=0xC0000000 L2CR spr 983=0x02000000 L3PM spr1018=0x8EA20004 L3CR spr1019=0x00000000 ICTC 0x0000=0x060800FF CPU Configuration 0x0120=0x00000050 CPU Mode 0x03B4=0x07C70273 CPU Pads Calibration 0x03C4=0x259EB1A2 Reset Sample (Low) 0x03D4=0x00550560 Reset Sample (High) 0x0160=0x00003B00 CPU Master Control 0x0150=0x22765430 CPU Interface Crossbar Control (Low) 0x0158=0x22765430 CPU Interface Crossbar Control (High) 0x0168=0x000100FF CPU Interface Crossbar Time Out 0x1400=0x4020026F SDRAM Configuration 0x1404=0x03114051 Dunit Control (Low) 0x1424=0x0B00F777 Dunit Control (High) 0x1408=0x11401110 SDRAM Timing (Low) 0x140C=0x00000007 SDRAM Timing (High) 0x1410=0x00000012 SDRAM Address Control 0x1414=0x00000000 SDRAM Open Pages Control 0x1418=0x00000000 SDRAM Operation 0x141C=0x00000022 SDRAM Mode 0x1420=0x00000000 Xtended DRAM Mode 0x1430=0x46636662 SDRAM Interface Crossbar Control (Low) 0x1434=0x66766566 SDRAM Interface Crossbar Control (High) 0x1438=0x000100FF SDRAM Interface Crossbar Timeout 0x14C0=0x07D9014A SDRAM Address/Control Pads Calibration 0x14C4=0x07D9014A SDRAM Data Pads Calibration 0x1480=0x00300000 DFCDL Configuration 0 0x1484=0x00D80100 DFCDL Configuration 1 0x14A0=0x00000000 DFCDL Probe MPX bus parity checking enabled CS enable was 0007FE7E CS 19 base=00001000 size=00000003 enable=0007FE7E devcs timing 81C497FF CS enable was 0007FE7E CS 5 base=0000F400 size=0000007F enable=0007FE5E FPGA devcs timing: 2, 2, 2 resetting the world world in reset MSR 00001072 starting the kernel 7767VIPX FAMILY SOFTWARE Version 2.2.0 Date Thu Nov 14 2013 13:15:20 Build Number 1384452920 twsi frequency 96144 Hz 0. BOOTVER=1 1. BOOTREV=0 2. BOOTBUILD=577 3. MEM_SIZE=0268435456 4. PROD=7867VIPX32X2 5. BRD=7700G4X 6. BRDREV=2 7. BRDBLD=6 8. ENET=1 9. SN=7132910006 10. MAC0=00:02:c5:16:8d:19 11. MAC1=00:02:c5:16:8d:1a Verify firmware contents [ OK ] Starting File System devcs timing 802460A3 CS enable was 0007FE5E CS 4 base=0000F500 size=00000000 enable=0007FE4E drive identification: general configuration: 0x44a cylinders: 7785 heads: 16 sectors: 63 serial: 20140320 00000F99 buffertype: 2 buffersize: 2 model: CF04NFXSF-FD000-D atavalid: 7 currcyls: 7785 currheads: 16 currsectors: 63 currsize0: -17040 currsize1: 119 lbasize: 7847280 opiomode: 0 dmasword: 0x0 dmamword: 0x7 eidepiomodes: 0x3 eidedmamin: 120 eidepioacked: 120 udmamode: 0x3f [ OK ] Starting Debugging [ OK ] devcs timing 802FFEEF flash identified boot area locked down low nv area locked high nv area locked flash init done block 0 at 0xf80000, block 1 at 0xfc0000 -----> first bytes f9 f8 -----> ERASED ff COPY fb VALID f9 INVALID f8 active block is 0, state VALID, next block is 1, state INVALID nvcfg_init nv_base:00000000 nv_cache_size:00040000 Starting LTC settings [ OK ] Starting Network net_init networking starting ETH1 out of reset sc_txbd = 4a81160, sc_txbdpool = 4a81144 Ethernet Unit Interrupt: 00000011 SMIdone hardware address 00:02:c5:16:8d:1a network ipaddr 192.168.8.225 mask 255.255.255.0 gw 192.168.9.1 bc 192.168.9.255 networking started [ OK ] @4a81098 sending gratuitous arp udp: allocated port 49152 page 0 / page 1 /snmppages.html page 2 /snmppages__Display.html Configuring file paths [ OK ] Loading FPGA(s)... Loading 7700g4x-32 FPGA... opening comp|cf:7700g4x-32 FPGA is Compressed misc: 00000002 80010000 PHY misc: 80080002 80110001 PHY link 7700g4x-32 FPGA loaded successfully. Loading 7700g2vx32-csx FPGA... opening comp|cf:7700g2vx32-csx FPGA is Compressed 7700g2vx32-csx FPGA loaded successfully. [ OK ] Starting PCI [ OK ] Starting Output FPGA [ OK ] Starting ASID Allocator [ OK ] Starting Display Manager Initializing Display Wall System Loading Display Wall Defaults GfxOutMgr::setOutputGrid cell dims 1x1 GfxOutMgr::setOutputGrid cell dims 1x1 GfxOutBase::setup id = 0 res = 1024,768 cells = 1,1 lsid/asid = 127,127 GfxOutBase::setup id = 1 res = 1024,768 cells = 1,1 lsid/asid = 126,126 [ OK ] Starting Video Manager Video Manager Reset About to start video manager thread Starting Input FPGA Video Manager Mainloop - started [ OK ] Starting Visin Settings [ OK ] Starting Memory Calibration bank = 0, try = 1 best_rdwen_sel = 1 lane delays [min:max (window size) = delay] lane = 0 DQS delay = 0:56 (57) = 28 DQ delay = 6:38 (33) = 22 lane = 1 DQS delay = 0:56 (57) = 28 DQ delay = 7:39 (33) = 23 lane = 2 DQS delay = 0:59 (60) = 29 DQ delay = 7:40 (34) = 23 lane = 3 DQS delay = 0:58 (59) = 29 DQ delay = 7:41 (35) = 24 lane = 4 DQS delay = 0:60 (61) = 30 DQ delay = 7:40 (34) = 23 lane = 5 DQS delay = 0:61 (62) = 30 DQ delay = 7:40 (34) = 23 lane = 6 DQS delay = 0:59 (60) = 29 DQ delay = 6:39 (34) = 22 lane = 7 DQS delay = 0:59 (60) = 29 DQ delay = 5:39 (35) = 22 lane = 8 DQS delay = 0:61 (62) = 30 DQ delay = 6:39 (34) = 22 lane = 9 DQS delay = 0:57 (58) = 28 DQ delay = 6:40 (35) = 23 lane = 10 DQS delay = 0:58 (59) = 29 DQ delay = 6:39 (34) = 22 lane = 11 DQS delay = 0:56 (57) = 28 DQ delay = 7:38 (32) = 22 lane = 12 DQS delay = 0:55 (56) = 27 DQ delay = 6:37 (32) = 21 lane = 13 DQS delay = 0:57 (58) = 28 DQ delay = 6:37 (32) = 21 lane = 14 DQS delay = 0:54 (55) = 27 DQ delay = 7:39 (33) = 23 lane = 15 DQS delay = 0:57 (58) = 28 DQ delay = 5:39 (35) = 22 bank = 1, try = 1 best_rdwen_sel = 1 lane delays [min:max (window size) = delay] lane = 0 DQS delay = 0:58 (59) = 29 DQ delay = 6:39 (34) = 22 lane = 1 DQS delay = 0:58 (59) = 29 DQ delay = 7:39 (33) = 23 lane = 2 DQS delay = 0:60 (61) = 30 DQ delay = 7:40 (34) = 23 lane = 3 DQS delay = 0:60 (61) = 30 DQ delay = 7:39 (33) = 23 lane = 4 DQS delay = 0:61 (62) = 30 DQ delay = 6:40 (35) = 23 lane = 5 DQS delay = 0:59 (60) = 29 DQ delay = 7:40 (34) = 23 lane = 6 DQS delay = 0:58 (59) = 29 DQ delay = 7:40 (34) = 23 lane = 7 DQS delay = 0:62 (63) = 31 DQ delay = 6:40 (35) = 23 lane = 8 DQS delay = 0:59 (60) = 29 DQ delay = 6:40 (35) = 23 lane = 9 DQS delay = 0:59 (60) = 29 DQ delay = 5:40 (36) = 22 lane = 10 DQS delay = 0:60 (61) = 30 DQ delay = 6:41 (36) = 23 lane = 11 DQS delay = 0:61 (62) = 30 DQ delay = 5:38 (34) = 21 lane = 12 DQS delay = 0:59 (60) = 29 DQ delay = 6:38 (33) = 22 lane = 13 DQS delay = 0:59 (60) = 29 DQ delay = 6:38 (33) = 22 lane = 14 DQS delay = 0:57 (58) = 28 DQ delay = 6:37 (32) = 21 lane = 15 DQS delay = 0:55 (56) = 27 DQ delay = 6:38 (33) = 22 Summary: bank 0: pass after 1 try. bank 1: pass after 1 try. [ OK ] Starting Genlock Dual Resolution Mode is Disabled! [ OK ] Initializing CSCs [ OK ] Initializing GLink Config Manager [ OK ] Initializing H/V Offset [ OK ] Initializing Frame Sync [ OK ] Initializing ASID Manager [ OK ] Starting Backgrounds [ OK ] Starting Warning manager [ OK ] Starting GPO Manager [ OK ] Starting Aux Serial Port No uart settings found. Using defaults [ OK ] Starting UMD Reader Initializing Image Video Processor 1 Ready to accept ImageVideo Protocol Image Video Processor 1 - Init Done. Using network. Initializing Image Video Processor 2 Ready to accept ImageVideo Protocol Image Video Processor 2 - Init Done. Using network. [ OK ] Starting VGPI System [ OK ] Starting Display wall system DisplayWallSys::loadProps: Loading settings from NV... WORKING CONFIGURATION OF DISPLAY WALL SYSTEM Output 0 Number of Canvases: 2 Wall Mode: 0 Resolution Std: 16 Refresh Rate: 1 H,V Offset: 0,0 Cell Dims: 1x1 Output 1 Number of Canvases: 2 Wall Mode: 0 Resolution Std: 16 Refresh Rate: 1 H,V Offset: 0,0 Cell Dims: 1x1 DisplayWallSys::loadProps3d: Loading 3D settings from NV... Output 0 3D mode:0 Output 1 3D mode:0 Valid wallcfg not found WORKING CONFIGURATION Output 0 Number of Canvases: 2 Wall Mode: 0 Resolution Std: 16 Refresh Rate: 1 (59.94 Hz) H,V Offset: 0,0 Cell Dims: 1x1 Output 1 Number of Canvases: 2 Wall Mode: 0 Resolution Std: 16 Refresh Rate: 1 (59.94 Hz) H,V Offset: 0,0 Cell Dims: 1x1 ACTIVE CONFIGURATION Output 0 Number of Canvases: 0 Wall Mode: 11 Resolution Std: 0 Refresh Rate: 0 (60.00 Hz) H,V Offset: 0,0 Cell Dims: 0x0 Output 1 Number of Canvases: 0 Wall Mode: 11 Resolution Std: 0 Refresh Rate: 0 (60.00 Hz) H,V Offset: 0,0 Cell Dims: 0x0 Tried scale 1 for out 0 resstd 16 refrate 1 cells 1x1 configure1to1Wall GfxCanvas::setup w 1920 h 1080 pitch 1920 PixBufAllocator::allocate: size = 2073600, cur_offset = 0 attachViewportToCell:writing to cell_to_viewport_[0][0]...done GfxOutMgr::setOutputGrid cell dims 1x1 PixBufAllocator::allocate: size = 2304000, cur_offset = 0 PixBufAllocator::allocate: size = 2304000, cur_offset = 2304000 Display Wall System - Update Tried scale 1 for out 1 resstd 16 refrate 1 cells 1x1 configure1to1Wall GfxCanvas::setup w 1920 h 1080 pitch 1920 PixBufAllocator::allocate: size = 2073600, cur_offset = 2073600 attachViewportToCell:writing to cell_to_viewport_[0][0]...done GfxOutMgr::setOutputGrid cell dims 1x1 PixBufAllocator::allocate: size = 2304000, cur_offset = 0 PixBufAllocator::allocate: size = 2304000, cur_offset = 2304000 Display Wall System - Update GfxOutMgr::applyConfiguration - res = 16 1,1,1,1,1 Genlock : 625/47.95 present on Ref 2 setGLinkEncScheme: 0 setLegacyFields: stppl 0 stlpf 0,0 Genlock : NTSC present on Ref 2 setGLinkEncScheme: 1 setLegacyFields: stppl 2200 stlpf 1125,0 SDIOutput : input_frame_rate_denominator = 1001 SDIOutput : input_frame_rate_numerator = 60000 SDIOutput : input_tlpf = 1125 SDIOutput : input_alpf = 1080 SDIOutput : input_appl = 1920 SDIOutput : tlpf = 1125 SDIOutput : v_act_start[0] = 21 SDIOutput : v_act_start[1] = 584 SDIOutput : v_act_stop[0] = 561 SDIOutput : v_act_stop[1] = 1124 SDIOutput : v_bit_start[0] = 561 SDIOutput : v_bit_start[1] = 1124 SDIOutput : v_bit_stop[0] = 21 SDIOutput : v_bit_stop[1] = 584 SDIOutput : f_bit_start = 564 SDIOutput : f_bit_stop = 1 SDIOutput : tspl = 2200 SDIOutput : h_end_of_line = 1919 SDIOutput : h_act_start = 0 SDIOutput : h_act_stop = 1920 SDIOutput : h_bit_start = 1920 SDIOutput : h_bit_stop = 2196 SDIOutput : h_sav_start = 2196 SDIOutput : h_sav_stop = 0 SDIOutput : h_eav_start = 1920 SDIOutput : h_eav_stop = 1924 SDIOutput : samps_per_pxl = 1 SDIOutput : frame_rate_num = 30000 SDIOutput : frame_rate_den = 1001 SDIOutput : tlpf = 1125 SDIOutput : v_act_start[0] = 20 SDIOutput : v_act_start[1] = 583 SDIOutput : v_act_stop[0] = 560 SDIOutput : v_act_stop[1] = 1123 SDIOutput : v_bit_start[0] = 560 SDIOutput : v_bit_start[1] = 1123 SDIOutput : v_bit_stop[0] = 20 SDIOutput : v_bit_stop[1] = 583 SDIOutput : f_bit_start = 563 SDIOutput : f_bit_stop = 1125 SDIOutput : tspl = 2200 SDIOutput : h_end_of_line = 1919 SDIOutput : h_act_start = 2199 SDIOutput : h_act_stop = 1919 SDIOutput : h_bit_start = 1919 SDIOutput : h_bit_stop = 2195 SDIOutput : h_sav_start = 2195 SDIOutput : h_sav_stop = 2199 SDIOutput : h_eav_start = 1919 SDIOutput : h_eav_stop = 1923 SDIOutput : samps_per_pxl = 1 SDIOutput : frame_rate_num = 30000 SDIOutput : frame_rate_den = 1001 SDIOutput : sdi_out_v_phase = 19 SDIOutput : sdi_sdram_h_phase = 280 SDIOutput : v_margin = 0 SDIOutput : v_start[0] = 21 SDIOutput : v_stop[0] = 561 SDIOutput : v_start[1] = 584 SDIOutput : v_stop[1] = 1124 SDIOutput : h_start = 0 SDIOutput : h_stop = 1920 SDIOutput : v_offset = 0 SDIOutput : h_offset = 0 SDIOutput : sdi_samp_freq_num = 000000019254D380h (6750000000d) SDIOutput : sdi_samp_freq_den = 000000000000005Bh (0000000091d) SDIOutput : sdi_clk_sel = 0 SDIOutput : sdi_clks_per_lock_int = 1100 SDIOutput : sdi_clks_per_lock_num = 0 SDIOutput : sdi_clks_per_lock_den = 1 SDIOutput : VPID = 85h-06h-00h-01h SDIOutput : VPID Insert Line 1 = 10 SDIOutput : VPID Insert Line 2 = 572 Programming video output clock. GfxOutMgr::applyConfiguration - res = 16 1,1,1,1,1 setGLinkEncScheme: 1 setLegacyFields: stppl 0 stlpf 0,0 setGLinkEncScheme: 1 setLegacyFields: stppl 2200 stlpf 1125,0 SDIOutput : input_frame_rate_denominator = 1001 SDIOutput : input_frame_rate_numerator = 60000 SDIOutput : input_tlpf = 1125 SDIOutput : input_alpf = 1080 SDIOutput : input_appl = 1920 SDIOutput : tlpf = 1125 SDIOutput : v_act_start[0] = 21 SDIOutput : v_act_start[1] = 584 SDIOutput : v_act_stop[0] = 561 SDIOutput : v_act_stop[1] = 1124 SDIOutput : v_bit_start[0] = 561 SDIOutput : v_bit_start[1] = 1124 SDIOutput : v_bit_stop[0] = 21 SDIOutput : v_bit_stop[1] = 584 SDIOutput : f_bit_start = 564 SDIOutput : f_bit_stop = 1 SDIOutput : tspl = 2200 SDIOutput : h_end_of_line = 1919 SDIOutput : h_act_start = 0 SDIOutput : h_act_stop = 1920 SDIOutput : h_bit_start = 1920 SDIOutput : h_bit_stop = 2196 SDIOutput : h_sav_start = 2196 SDIOutput : h_sav_stop = 0 SDIOutput : h_eav_start = 1920 SDIOutput : h_eav_stop = 1924 SDIOutput : samps_per_pxl = 1 SDIOutput : frame_rate_num = 30000 SDIOutput : frame_rate_den = 1001 SDIOutput : tlpf = 1125 SDIOutput : v_act_start[0] = 20 SDIOutput : v_act_start[1] = 583 SDIOutput : v_act_stop[0] = 560 SDIOutput : v_act_stop[1] = 1123 SDIOutput : v_bit_start[0] = 560 SDIOutput : v_bit_start[1] = 1123 SDIOutput : v_bit_stop[0] = 20 SDIOutput : v_bit_stop[1] = 583 SDIOutput : f_bit_start = 563 SDIOutput : f_bit_stop = 1125 SDIOutput : tspl = 2200 SDIOutput : h_end_of_line = 1919 SDIOutput : h_act_start = 2199 SDIOutput : h_act_stop = 1919 SDIOutput : h_bit_start = 1919 SDIOutput : h_bit_stop = 2195 SDIOutput : h_sav_start = 2195 SDIOutput : h_sav_stop = 2199 SDIOutput : h_eav_start = 1919 SDIOutput : h_eav_stop = 1923 SDIOutput : samps_per_pxl = 1 SDIOutput : frame_rate_num = 30000 SDIOutput : frame_rate_den = 1001 SDIOutput : sdi_out_v_phase = 19 SDIOutput : sdi_sdram_h_phase = 280 SDIOutput : v_margin = 0 SDIOutput : v_start[0] = 21 SDIOutput : v_stop[0] = 561 SDIOutput : v_start[1] = 584 SDIOutput : v_stop[1] = 1124 SDIOutput : h_start = 0 SDIOutput : h_stop = 1920 SDIOutput : v_offset = 0 SDIOutput : h_offset = 0 SDIOutput : sdi_samp_freq_num = 000000019254D380h (6750000000d) SDIOutput : sdi_samp_freq_den = 000000000000005Bh (0000000091d) SDIOutput : sdi_clk_sel = 0 SDIOutput : sdi_clks_per_lock_int = 1100 SDIOutput : sdi_clks_per_lock_num = 0 SDIOutput : sdi_clks_per_lock_den = 1 SDIOutput : VPID = 85h-06h-00h-01h SDIOutput : VPID Insert Line 1 = 10 SDIOutput : VPID Insert Line 2 = 572 Programming video output clock. [ OK ] Starting Output Vertical ISR [ OK ] Starting Input Vertical ISR Success: OP47 configured for VANC processing [ OK ] Starting Audio ISR [ OK ] Starting Scaler ISR intsc_init HFILT page = 0 VFILT page = 12352 HFILT page = 24704 VFILT page = 37056 Done HFILT page = 0 VFILT page = 12352 HFILT page = 24704 VFILT page = 37056 Done [ OK ] Starting Nielsen UDP Process [ OK ] Initialize GFX Service Routine [ OK ] Starting Font System [ OK ] Starting Background System [ OK ] Starting Image System [ OK ] Starting Trigger Names [ OK ] Starting Stream Manager [ OK ] Starting Thumbnails udp: allocated port 49153 [ OK ] Starting GPI System [ OK ] Starting Ticker [ OK ] Starting EMR [ OK ] Starting Video Loss Image [ OK ] Starting Cursor Image readHeader: cf:cursor_fill.bmp: error -1 [ OK ] Starting NEaT Service [ OK ] Starting Database [ OK ] Starting Backgrounds [ OK ] Starting Onscreen Control [ OK ] Starting Renderer render init [ OK ] Starting FTPd [ OK ] Starting SNMP Agent Notification reqID initialized to 11840 Error bringing up SNMP agent Starting Loading RGB Tables [ OK ] Initializing Fault Properties [ OK ] Initializing Video Properties [ OK ] Initializing Miscellaneous Properties udp: allocated port 49154 udp: allocated port 49155 udp: allocated port 49156 udp: allocated port 49157 [ OK ] Starting Fault Collector [ OK ] 3G SDI Output Optimization is Disabled. Starting Board Status [ OK ] Starting Server Manager [ OK ] Starting Global Timers [ OK ] Starting Discovery [ OK ] Starting Periodic Saver [ OK ] Saving server settings ... done Starting NNS Service [ OK ] Board status thread starting... Starting Video Detect Thread [ OK ] Starting FPGA Service Routine [ OK ] Starting Input Router SDIOutput : tlpf = 1125 SDIOutput : v_act_start[0] = 20 SDIOutput : v_act_start[1] = 583 SDIOutput : v_act_stop[0] = 560 SDIOutput : v_act_stop[1] = 1123 SDIOutput : v_bit_start[0] = 560 SDIOutput : v_bit_start[1] = 1123 SDIOutput : v_bit_stop[0] = 20 SDIOutput : v_bit_stop[1] = 583 SDIOutput : f_bit_start = 563 SDIOutput : f_bit_stop = 1125 SDIOutput : tspl = 2200 SDIOutput : h_end_of_line = 1919 SDIOutput : h_act_start = 2199 SDIOutput : h_act_stop = 1919 SDIOutput : h_bit_start = 1919 SDIOutput : h_bit_stop = 2195 SDIOutput : h_sav_start = 2195 SDIOutput : h_sav_stop = 2199 SDIOutput : h_eav_start = 1919 SDIOutput : h_eav_stop = 1923 SDIOutput : samps_per_pxl = 1 SDIOutput : frame_rate_num = 30000 SDIOutput : frame_rate_den = 1001 SDIOutput : sdi_out_v_phase = 19 SDIOutput : sdi_sdram_h_phase = 280 SDIOutput : v_margin = 0 SDIOutput : v_start[0] = 21 SDIOutput : v_stop[0] = 561 SDIOutput : v_start[1] = 584 SDIOutput : v_stop[1] = 1124 SDIOutput : h_start = 0 SDIOutput : h_stop = 1920 SDIOutput : v_offset = 0 SDIOutput : h_offset = 0 SDIOutput : sdi_samp_freq_num = 000000019254D380h (6750000000d) SDIOutput : sdi_samp_freq_den = 000000000000005Bh (0000000091d) SDIOutput : sdi_clk_sel = 0 SDIOutput : sdi_clks_per_lock_int = 1100 SDIOutput : sdi_clks_per_lock_num = 0 SDIOutput : sdi_clks_per_lock_den = 1 SDIOutput : VPID = 85h-06h-00h-01h SDIOutput : VPID Insert Line 1 = 10 SDIOutput : VPID Insert Line 2 = 572 [ OK ] 7767VIPX FAMILY SOFTWARE Version 2.2.0 Date: Thu Nov 14 2013 13:15:20 --------------------------------------------------------- | Main Menu | | (7867VIPX32X2 2.2.0) | --------------------------------------------------------- (1) Network Configuration (2) Onboard Server Configuration (3) SNMP Configuration (4) Under Monitor Display Setup (5) Auxiliary Serial Port Setup (6) SNTP Source (7) Genlock/Cascade Raster Offset (8) Cascade Configuration (9) GLink Settings (10) Video Utilities (11) SDI Output Settings (12) Engineering/Debug (X) Exit >