v2.0.1	- 06/10/2019	MeterLstnDBuf.v fix for VOX; added 'posedge' for S11_MeterAudio to
			create missing register; was built without register
v2.0.0	- Control Bus Metastability Fix	
		ctr_fifo_v4 	- fixed New_Rx_Data_Pulse clock crossing
				- added Rx_New_Msg_Clr resets Rx FIFO on each Listen access
				** Error caused lost bytes in Rx FIFO & message length counter
				** Error caused missing 1st byte & message rx interrupt
		rx_sync_v4	- fixed Contr_Bus_listen_Clk clock crossing
				** Error caused bit miss-alignment within Listen Byte
v1.1.4	- SignalTap with state-based triggering for CntlBus error
v1.1.3	- missing deleted 'else' in state machine; fixed
v1.1.2	- v1.1.1 fails. the logic is wrong i need !(!codec_reset_n || !frame_delay_reset_n)
	  but the original logic was (codec_reset_n && frame_delay_reset_n) and it should have worked
	  built a register to connect to the loan pin instead of combinatorial delay
v1.1.1	- delay rst logic error; fixed (!codec_reset_n || !frame_delay_reset_n)
v1.1.0	- delayed release of adc_codec_rst until rx_1x_clk rising edge;
	  lrclk starts high so the clk counter has begun running before this time
	  needed for the case where both master card slot clocks are reset simultaneously
v1.0.07 - delayed release of adc_codec_rst until start_dly of 1.4ms is completed.
v1.0.06	- check for false positives added to tdm_clk_good
v1.0.05	- tdm_clk_good added; compared tdm_clk_cnt in 1us to determine clock speed
	  once tdm_clk_good is valid, delayed lr_clk and bitclk from tdm_start with start dly = 1.4ms
V1.0.04 - delayed lr_clk and bitclk from tdm_start with start dly = 1.4ms
V1.0.03	- talk i2s logic into clk_72_72mhz domain
	  added tdm_clk pll lock max = 0.5ms; start dly = 1.4ms
V1.0.0_release 	-Built V1.0.01 for release
		 tdm clk start-up delay.		
V1.0.02 - moved talk i2s logic into clk_72_72mhz domain
	  still had tdm clk startup noise when switching
	  over both tdm_clk cards simultaneously
V1.0.01 - Control Bus start-up error seen on V1.0.00
	  Rerouted by setting compiler setting 
		= Performance (Aggressive)
		= Fitter Effort (Auto Fit)		
V1.0.00_test	- Fix for Adam Clock Switch Over 
		  Delayed the talk i2s sm until the tdm_clk pll locked
		  tdm_clk pll lock max = 0.5ms; start dly = 1.4ms
		  Quartus v15.1 compiled
		  tdm_clk = global needed to route in timing
V0.1.00	- Quartus Prime v15.1 compiled
v0.0.17	- Change audio test module sink memory write,
	  will only write when enabled and !full
v0.0.10	- Added test audio for channel 0
v0.0.9	- Same as v0.0.8.2
	  But passed hold time
v0.8.2	- tdm_oe_l output on neg edge of tdm_clk with output delay added hold is +2
	- results in a 4.4ns tco
v0.8.1	- tdm_oe_l output on neg edge of tdm_clk with output delay added hold is -1.5
	- results in a 8ns tco
v0.0.8	- tdm_oe_l output on neg edge of tdm_clk with output delay added hold is -4.5
	- results in a 10.5ns tco
v0.0.7	- tdm_oe_l output on neg edge of tdm_clk
v0.0.6	- Add tdm_clk pll to phase adjust tdm_oe_l; also mixer runs off the delay compensated pll
v0.0.5	- revert to the 0.0.3 version
v0.0.4	- 32 rx-256x-clk delay of the parallel port audio read & write
	- falling rx-256x-clk delay of bit_clk from lr_clk
v0.0.3	- UART sin weak pull-up added
v0.0.2	-led daughter card bit reversal
		- data
		- cs
		- soft button
	- fix gain 1 clock too late
	  seen as chan 1 gain -> chan 2 audio & chan 2 gain -> chan 3; etc
	  changed gain address 1 clock earlier	
V0.0.1	-AAP-16 Initial Version